The invention relates to an electronic circuit comprising an amplifier comprising an output terminal for supplying an output signal to a load, the amplifier comprising an output transistor having a first main terminal coupled to a supply voltage terminal of the amplifier, a second main terminal coupled to the output terminal, and a control terminal.
Such an electronic circuit is known from the general state of the art as shown in FIG. 1. The known circuit comprises an amplifier having an amplifying complementary (class-AB) output stage driven by a class-A amplifying stage. The output stage may be followed by a unity-voltage-gain (follower-type) output stage (not drawn). Such an amplifier is e.g. used in integrated drivers for CRT""S.
A high-side output branch includes n-type transistor N1 in common-drain configuration and p-type transistor P1 in common gate configuration. The gate of P1 is coupled to the positive supply voltage by means of a bias voltage source E1 of appropriate value. In almost every technology the speed of the p-type transistor is worse than than of the n-type transistor, among others due to the difference in carrier mobility""s. In applications, where the speed is at the edge of what the technology offers, the p-type transistor is preferably used in common-gate configuration, as the bandwidth of the transfer from source signal current to drain signal current approaches the transistor""s transition frequency fT. A low-side output transistor N2 is biased in common-source configuration. The amplifying stage consists of differential transconductor (shown as a box gm in the lower part) loaded by two current sources J1 and J2. The differential transconductor converts the differential input voltage Vin+xe2x88x92Vinxe2x88x92 to a differential output current Iout+xe2x88x92Ioutxe2x88x92=gm (Vin+xe2x88x92Vinxe2x88x92), in which gm is the transconductance. The bias current value of both current sources J1 and J2 is controlled by a common-mode control loop (not shown), which essentially controls the quiescent current in the output transistors N1, P1 and N2.
The voltage gain of output transistors P1 and N2 can be large provided that they are biased in saturation and not in the linear region. Clamping circuits can monitor the drain-to-gate voltage and take appropriate action whenever these voltages tend to enter the linear region.
FIG. 2 shows a known clamp circuit. This type of clamp circuit is generally denoted as a xe2x80x9cBakerxe2x80x9d clamp. In normal operation the collector-base junction is reverse biased, diode D1 is reversed biased and diode D2 is forward biased. Whenever the collector voltage tends to drop to below the base voltage the diode D1 is forward biased. The bipolar transistor N1 then operates at near-zero collector-base voltage and the excess base drive current is bypassed via D1. As a results the bipolar transistor N1 is kept out of saturation. The xe2x80x9cBakerxe2x80x9d clamp principle can also be applied to MOS transistors.
FIG. 3 shows a generalized form of the clamp circuit according to FIG. 2. The source of transistor NN is connected to the drain of the output transistor N2. The gate of NN is connected to an appropriate voltage level, here symbolized by Eb1. In normal operation transistor NN is cut off. Whenever N2""s drain voltage decreases to more than a threshold voltage below NN""s gate voltage, transistor NN becomes conductive and its increasing drain current can be used in the driving circuit DRV to reduce the gate drive of output transistor N2 to keep N2 in saturation.
FIG. 4 shows another generalized form of the clamp circuit according to FIG. 2. The gate of transistor PP senses the drain voltage of output transistor N2. In normal operation the transistors NN and PP are cut off. Whenever N2""s drain voltage decreases too much (to be set by the value of Eb1 and threshold voltages of NN and PP) the transistor pair NN/PP becomes conductive and its increasing channel current can be used in driving circuit DRV to reduce the gate drive of output transistor N2. Contrary to the circuit principle of FIG. 3 the clamping current is not conducted by the output transistor N2.
FIG. 5 shows an input signal attenuator, known from U.S. Pat. No. 5,304,865. It comprises a MOS transistor NN and a resistor R3, to be used in conjunction with a comparator. The source node of the MOS transistor NN can be used to sense the drain voltage. As long as this voltage is higher than the gate voltage, the MOS transistor is in saturation and the channel is cut off. The source voltage is approximately equal to the gate voltage. If the drain voltage falls below the gate bias voltage, the MOS transistor NN is rendered conductive in the linear range and the source voltage follows the drain voltage.
For some applications it can (unintentionally) occur that the output voltage Vout at the output terminal OUT is so low that the transistor N2 enters its linear operating state. This causes the amplifier to react relatively slow. A similar situation, with regard to the combined transistor pair N1/P1, occurs when the output voltage Vout becomes too high. The former situations can occur when the amplifier is for instance used as a CRT-cathode-driving amplifier. High voltages characterize it: the applied supply voltage Esup and the required output voltage Vout swing exceed the allowable gate-source voltage of for instance the transistor N2 (some 20V) by far. The supply voltage Esup can range between 50V and 250V and the required peak-to-peak output voltage Vout swing ranges from 40V (monochrome monitors), via 100-150V (color television) to 200V (color projection television). These applications require a speed (bandwidth, slew rate, rise time etc.) which is at the edge of what technology offers. It therefore is of prime importance that the parasitic capacitances at the gates of N1 and N2 in FIG. 1 are minimized.
In order to get the highest speed as possible it is necessary to avoid the output voltage Vout to become too high or too low, so that the transistor N2 and the combined transistor pair N1/P1 are kept in their normal state of operation. In prior art circuits this is accomplished by the application of, for instance, one of the circuits as shown in FIGS. 2-4. Further the requirements for a low power consumption dictates low bias currents.
In the xe2x80x9cBakerxe2x80x9d clamp of FIG. 2 the clamping diode D1 needs to withstand a reverse-bias voltage far exceeding 10V. This implies that the shallow-p (SP) to n-epitaxial layer must be used. In a junction-isolated technology forward biasing of the SP-epi junction has the disadvantage that a parasitic substrate pnp transistor is activated: the SP region acts as emitter, the epilayer as base and the p-type substrate as collector. To reduce the pnp current gain the SP-epi junction has to be surrounded as much as possible by high-dope n-type material (buried-n and deep-n diffusions). The consequences are severe: the allowable reverse-bias voltage across the diode D1 is reduced, and the layout size and thus parasitic capacitances are increased. For high reverse-bias voltages a series connection of more diodes might be needed, which increases layout size and parasitic capacitances even more. Thus the xe2x80x9cBakerxe2x80x9d clamp of FIG. 2 offers too high parasitic capacitance and cannot be applied if a high speed is important.
The generalized xe2x80x9cBakerxe2x80x9d clamp principles of FIG. 3 and FIG. 4 cannot be be applied, because the clamping transistors are tied to the high-voltage-swing node with their gate or their source, which is not allowed in normal IC-processes. (The transistors can be damaged).
For detecting whether the output voltage Vout is too low (or too high), the circuit shown in FIG. 5 can be used (in which the source voltage of the MOS-transistor NN forms an input voltage for a comparator).
It is an object of the invention to provide an electronic circuit provided with an amplifier having a high (transient) speed irrespective whether the amplifier is applied in a low, medium, or high voltage electronic system.
To this end, according to the invention, an electronic circuit is provided comprising:
an amplifier comprising an output terminal for supplying an output signal to a load, the amplifier comprising an output transistor having a first main terminal coupled to a supply voltage terminal of the amplifier, a second main terminal coupled to the output terminal, and a control terminal; and
control means for avoiding the output transistor to enter its linear state, the control means being arranged to reduce a control voltage between the control terminal and the first main terminal when an output voltage between the second main terminal and the first main terminal is below a defined level.
The invention is based on the insight that if the voltage across the output transistor becomes too low, as a consequence of which the output transistor unintentionally enters its linear operating state, this is in fact caused by a too high control voltage at the output transistor. Thus by reducing the control voltage, when the voltage across the main current path of the output transistor tends to become too low, the voltage across the said main current path will no longer decrease. (In fact a negative feedback loop is created) Thus the output transistor stays in its normal state of operation thereby avoiding the amplifier to react with reduced speed.
In an embodiment of a circuit according to the invention the control means comprises level detection means for, during operation of the electronic circuit, supplying a substantial change in voltage difference when the output voltage becomes lower than the defined level, and transconductor means for supplying a control current to the amplifier for reducing the control voltage on respond to the control current. Due to the fact that the level detection means delivers a substantial, thus not a very small, change in voltage difference it is assured that the control voltage is only adapted when needed, and not by an undesired offset-voltage, which may for instance be in the transconductor means. This makes the circuit easier to design (less sensitive to design parameters) and more reliable.